Nand flash memory

ABSTRACT

A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Division of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 12/719,686, filed Mar. 8, 2010,which is a Continuation Application of U.S. application Ser. No.11/836,378, filed Aug. 9, 2007, which is based upon and claims thebenefit of priority from the prior Japanese Patent Application No.2006-221997, filed on Aug. 16, 2006, the entire contents of each ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a NAND flash memory.

2. Background Art

Data writing to a non-volatile memory cell, such as a NAND flash memory,is achieved by changing the threshold of the cell by applying a highelectrical field to the cell to cause trapping of an electron into anoxide film. On the other hand, data reading is achieved by using thevariation in threshold. This principle holds true for multi-level memorycells (see Japanese Patent Laid-Open Publication No. 2001-332093, forexample).

As an example of prior art, a reading operation of a NAND flash memory(of shielded bit line architecture) will be shortly described.

The source line and the well of a cell are set at a potential “V_(SS)”(0 V), and a potential “VSG” (“V_(DD)”+“Vth”) (about 4 V), which allowstransfer of “V_(DD)” (2.5 V), is applied to the gate “BLPRE” of then-type MOS transistor of the sense amplifier. And, a potential of 0.7V+Vth is applied to the gate “BLCLAMP” of the n-type MOS transistor thatconnects the sense amplifier and the bit line to each other, therebypre-charging the bit line of the cell to a potential of 0.7 V.

However, not all the bit lines are charged to 0.7 V. The bit lines arealternately charged to 0.7 V and 0 V, and a half of the bit lines are tobe read.

During reading, a bit line amplitude occurs due to the data. Adjacentbit lines are affected by the bit line amplitude due to the capacitivecoupling. Thus, the bit lines are shielded to prevent data modificationby data in the adjacent cells.

After the pre-charge, the gate “BLCLAMP” is set at 0 V, and the bitlines and the sense amplifier are separated from each other.

A desired potential “VCGRV” is applied to a word line to be read, apotential “VREAD” (about 5 V), which allows turn-on without fail, isapplied to the other word lines and the drain-side select gate line, andfinally the potential “VREAD” is applied to the source-side select gateline.

Thus, if the cell to be read is turned on, a cell current flows, and thepotential of the bit line approaches 0 V. If the cell to be read isturned off, no cell current flows, so that the potential of the bit lineremains at the pre-charge voltage (0.7 V).

The gate “BLPRE” is raised again, and the node “TDC” connected to thelatch circuit of the sense amplifier is pre-charged to “V_(DD)”. Afterthat, the gate “BLCLAMP” is set at “VSEN” (0.35 V+Vth).

Compared with the capacitance of the bit line, the capacitance of thenode “TDC” is low. Therefore, when the cell is turned on, if thepotential of the bit line is lower than 0.35 V, charge sharing occurs,and the potential at the node “TDC” becomes equal to the potential ofthe bit line.

When the cell is turned off, if the potential of the bit line is equalto 0.7 V, the transistor having the gate “BLCLAMP” remains in the offstate because the threshold thereof cannot be exceeded, and thus, thepotential at the node “TDC” remains at “V_(DD)”. By raising thepotential at the gate of the n-type MOS transistor between the latchcircuit and the node “TDC”, the potential at the node “TDC” istransferred to the latch circuit, thereby designating H/L.

The threshold of the cell can be identified by changing the voltage“VCGRV” of the word line of the cell to be read. For example, if thecell has two thresholds, the cell can store two values. If the cell hasfour thresholds, the cell can store four values.

Thus, if the cell has 16 thresholds, the cell can store 16 values. Tostore 16 values, the retention margin of each threshold is reduced.Although the range of thresholds can be expanded to higher thresholds,higher thresholds lead to higher writing voltage and higher readingvoltage.

If the writing or reading voltage increases, the writing or readingoperation becomes more likely to be disturbed. As a result, there is aproblem that the preset thresholds are also disturbed and shifted. Thethreshold shift causes erroneous reading.

Thus, it can be contemplated that, by setting a negative threshold, theretention margin can be enhanced without increasing the disturbanceduring reading or writing. Alternatively, this can be achieved byapplying a negative potential to the word line.

However, the connection of the well is modified to enable transfer ofthe negative potential, and thus, the number of steps disadvantageouslyincreases.

To overcome this disadvantage, the source line or p-type well of thecell can be biased. In this case, even if only a positive voltage isapplied to the word line, the actual threshold “VGS” of the cell (thepotential of the word line minus the potential of the source line of thecell) can be negative. That is, the threshold distribution can be formedalso in the negative region.

However, biasing the source line or p-type well of the cell results inbiasing of the source line or p-type well of other cells that don't needto be charged. Thus, there is a problem that the current consumptionincreases.

In addition, there is a problem that the reading or writing timeincreases because charging the source line or p-type well of the celltakes additional time (this is because the writing time includes thetime required for verification, which is equivalent to reading, afterwriting).

If the source line or p-type well of the cell is not biased, onlyrequired is the charge for charging the bit line.

On the other hand, if the source line or p-type well of the cell isbiased, an amount of charge is required to bias the source line orp-type well of the cell to a non-selected bit line (shielded bit line),in addition to the charge required for charging the bit line.

Biasing the source line or p-type well of the cell takes about 10 μs,for example, and therefore, the reading time increases accordingly.

SUMMARY OF THE INVENTION

According one aspect of the present invention, there is provided: a NANDflash memory that is read while a selected bit line and a non-selectedbit line are adjacent to each other, comprising a memory cell arrayhaving a plurality of blocks each of which is composed of a plurality ofmemory cell units, each of said memory cell units having a plurality ofelectrically rewritable memory cells that are connected to each otherand composed of a p-type well surrounded by an n-type well formed in ap-type semiconductor substrate, drain-side select gate transistors eachof which connects a memory cell unit to a bit line and is connected to adrain-side select gate line at the gate thereof, and source-side selectgate transistors each of which connects a memory cell unit to a sourceline and is connected to a source-side select gate line at the gatethereof; a row decoder that is connected to word lines, the drain-sideselect gate lines and the source-side gate line of said memory cellarray, and applies a signal voltage to word lines, the drain-side selectgate lines and the source-side gate line of said memory cell array forselecting a block; and a sense amplifier that is controlled by a columndecoder and makes a selection from said bit lines of said memory cellarray, wherein, in a block that is not selected by said row decoder,said bit line selected by said sense amplifier is charged in a statewhere the drain-side select gate line, the source-side select gate lineand the p-type semiconductor substrate are set at a ground potential,and the source lines, the n-type wells, the p-type wells and a bit linethat is not selected by said sense amplifier are in a floating state.

According another aspect of the present invention, there is provided: aNAND flash memory that is read while a selected bit line and anon-selected bit line are adjacent to each other, comprising a memorycell array having a plurality of blocks each of which is composed of aplurality of memory cell units, each of said memory cell units having aplurality of electrically rewritable memory cells that are connected toeach other and composed of a p-type well surrounded by an n-type wellformed in a p-type semiconductor substrate, drain-side select gatetransistors each of which connects a memory cell unit to a bit line andis connected to a drain-side select gate line at the gate thereof, andsource-side select gate transistors each of which connects a memory cellunit to a source line and is connected to a source-side select gate lineat the gate thereof; a row decoder that is connected to word lines, thedrain-side select gate lines and the source-side gate line of saidmemory cell array, and applies a signal voltage to word lines, thedrain-side select gate lines and the source-side gate line of saidmemory cell array for selecting a block; and a sense amplifier that iscontrolled by a column decoder and makes a selection from said bit linesof said memory cell array, wherein in a block that is not selected bysaid row decoder, said bit line selected by said sense amplifier ischarged to a first potential at the same time as the drain-side selectgate line, the source-side select gate line and the p-type semiconductorsubstrate being set at a ground potential, and the source lines, then-type wells, the p-type wells and the bit line that is not selected bysaid sense amplifier being charged to a second potential that is betweensaid first potential and said ground potential.

According further aspect of the present invention, there is provided; aNAND flash memory that is read while a selected bit line and anon-selected bit line are adjacent to each other, comprising a memorycell array having a plurality of blocks each of which is composed of aplurality of memory cell units, each of said memory cell units having aplurality of electrically rewritable memory cells that are connected toeach other and composed of a p-type well surrounded by an n-type wellformed in a p-type semiconductor substrate, drain-side select gatetransistors each of which connects a memory cell unit to a bit line andis connected to a drain-side select gate line at the gate thereof, andsource-side select gate transistors each of which connects a memory cellunit to a source line and is connected to a source-side select gate lineat the gate thereof; a row decoder that is connected to word lines, thedrain-side select gate lines and the source-side gate line of saidmemory cell array, and applies a signal voltage to word lines, thedrain-side select gate lines and the source-side gate line of saidmemory cell array for selecting a block; and a sense amplifier that iscontrolled by a column decoder and makes a selection from said bit linesof said memory cell array, wherein in a block that is not selected bysaid row decoder, said bit line selected by said sense amplifier ischarged to the first potential while the drain-side select gate line,the source-side select gate line and the p-type semiconductor substrateare being set at a ground potential, and the source lines, the n-typewells, the p-type wells and the bit line that is not selected by saidsense amplifier are being charged to a second potential that is betweensaid first potential and said ground potential.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of essential parts ofa NAND flash memory 100 according to an First Embodiment of the presentinvention, which is an aspect of the present invention;

FIG. 2 is a diagram showing a configuration of essential parts of amemory cell array of the NAND flash memory 100 shown in FIG. 1;

FIG. 3 is a diagram showing a configuration of essential parts of asense amplifier of the NAND flash memory 100 shown in FIG. 1;

FIG. 4 is a timing chart for illustrating the read operation of the NANDflash memory 100;

FIG. 5 is a diagram showing a configuration of essential parts includinga voltage generating circuit that applies the voltage Vs;

FIG. 6A is a graph showing a relationship between time and voltageapplied to the selected bit line or the like of the NAND flash memory100 during the reading operation according to the First Embodiment;

FIG. 6B is a graph showing another relationship between time and voltageapplied to the selected bit line or the like of the NAND flash memory100 during the reading operation according to the First Embodiment;

FIG. 7 is a diagram showing a model of a cross-sectional structure ofthe NAND flash memory 100;

FIG. 8 is a diagram showing potentials at the parts of the NAND flashmemory 100 shown in FIG. 7 and capacitances between the parts;

FIG. 9 is a circuit diagram showing a configuration of a NAND flashmemory 200 according to the Second Embodiment, which is an aspect of thepresent invention, including blocks and a row decoder;

FIG. 10 is a circuit diagram showing a configuration of a NAND flashmemory 300 according to the Third Embodiment of the present invention,which is an aspect of the present invention, including blocks and a rowdecoder;

FIG. 11 is a circuit diagram showing a push-pull circuit, which is avoltage generating circuit used in the Fourth Embodiment of the presentinvention; and

FIG. 12 is a graph showing a relationship between time and voltageapplied to a selected bit line or the like of a NAND flash memory 100during reading operation according to the Fourth Embodiment.

DETAILED DESCRIPTION

According to the prior art described above, when reading by biasing thesource line or p-type well of a NAND flash memory cell, the bit line ischarged after the source line or p-type well of the cell is biased. Inthis case, an amount of charge is required not only to charge the bitline but also to bias the source line or p-type well of the cell. Theamount of charge leads to an increase in current and pre-charge time andthus to degradation in performance of the NAND flash memory.

Thus, for a NAND flash memory according to an aspect of the presentinvention, bit lines are charged while source lines, p-type wells andnon-selected bit lines of cells are kept in a floating state. As aresult, in a coupling state, the source lines, the p-type wells and thenon-selected bit lines of the cells settle at a potential that isdetermined by the coupling ratio. Thus, the amount of charge that wouldotherwise be required for charging thereof is not required, and thecharging operation can be ended without any extra time. Therefore, thecharging can be achieved in a short time.

Thus, the threshold distribution can be formed also in the negativeregion while preventing an increase in current and pre-charge time.

In the following, embodiments of the present invention will be describedwith reference to the drawings.

First Embodiment

FIG. 1 is a block diagram showing a configuration of essential parts ofa NAND flash memory 100 according to a First Embodiment of the presentinvention, which is an aspect of the present invention. FIG. 2 is adiagram showing a configuration of essential parts of a memory cellarray of the NAND flash memory 100 shown in FIG. 1. FIG. 3 is a diagramshowing a configuration of essential parts of a sense amplifier of theNAND flash memory 100 shown in FIG. 1.

As shown in FIGS. 1 and 2, a memory cell array 1 has a plurality of cellunits arranged in an array. On the memory cell array 1, word lines(control gate lines) “WL” extending in a row direction and bit lines “BL(BLe, BLo)” extending in a column direction are disposed. The word lines“WL” are connected to a row decoder 2, and the bit lines “BL” areconnected to a sense amplifier 3, which has a latch circuit fortemporarily storing write data and read data.

The memory cell array 1 has a plurality of blocks 1 a. A block 1 a iscomposed of a plurality of memory cell units composed of a plurality ofmemory cells 1 b connected to each other, drain-side select gatetransistors 1 c that connect the memory cell units to the respective bitlines “BL” and are connected to a drain-side select gate line “SGD” atthe respective gates thereof, and source-side select gate transistors 1d that connect the memory cell units to respective source lines “CELSRC”and are connected to a source-side select gate line SGC at therespective gates.

As described above, each cell unit is composed of a plurality ofelectrically rewritable memory cells 1 b, which have a p-type well“PWELL” surrounded by an n-type well NWEL formed in a p-typesemiconductor substrate “Psub”.

The sense amplifier 3 is connected to an I/O buffer 8 via a column gate(column select switch) 4. The column gate 4 is controlled by an outputsignal from a column decoder 5. That is, the sense amplifier 3 iscontrolled by the column decoder 5 and makes a selection from the bitlines “BL” in the memory cell array 1.

As shown in FIG. 3, the sense amplifier 3 has a latch circuit 3 a forstoring the potential at a node “TDC”, a transistor 3 b connectedbetween the node “TDC” and bit lines “BLe”, “BLo”.

Furthermore, the sense amplifier 3 has a capacitor 3 c connected to thenode “TDC”, a transistor 3 d for controlling a voltage VPRE applied tothe node “TDC”, a transistor 3 e connected between the node “TDC” andthe latch circuit 3 a.

In FIG. 3, the potentials at “BLSe” and “BLSo” are controlled by acontrol circuit 7 in such a manner that transistors 7 a and 7 b arealternately turned on. Thus, when the transistor 7 a is turned on,“SABL” is electrically connected to the bit line “BLe”, and when thetransistor 7 b is turned on, “SABL” is electrically connected to the bitline “BLo”. In other words, the bit lines “BLe” and “BLo” arealternately selected by controlling the potentials at “BLSe” and “BLSo”.

Furthermore, the potentials at “BIASe” and “BIASo” are controlled by thecontrol circuit 7, and transistors 7 c and 7 d are alternately turned onso that the potential of a control line “BLCRL” is supplied to the bitline not selected.

As shown in FIG. 1, a booster circuit 6 generates voltages required in awrite mode, an erase mode and a read mode. For example, when writingdata, the booster circuit 6 generates a write voltage and supplies thewrite voltage to the row decoder 2.

The row decoder 2 is connected to the word lines “WL” and the selectgate lines of the memory cell array 1 and applies a signal voltage tothe word lines “WL” and the select gate lines of the memory cell array 1for selecting a block. A row address signal is input to the row decoder2, and a column address signal is input to the column decoder 5.

The control circuit 7 controls the operation of the row decoder 2, thecolumn gate 4 and the column decoder 5 depending on the operation mode.For example, when writing data, the control circuit 7 controls thetiming of switching of the potential supplied to the word lines “WL” andthe select gate lines “SGD” and “SGS”.

Now, a read operation of the NAND flash memory 100 configured asdescribed above will be described. FIG. 4 is a timing chart forillustrating the read operation of the NAND flash memory 100.

In the following, with reference to FIGS. 2 to 4, there will beparticularly described a reading method in a case where the source line“CELSRC” and the p-type semiconductor substrate “PWELL” of a cell arebiased to a potential “Vs” in order to form the cell thresholddistribution in the negative region.

First, the source line “CELSRC” and the p-type semiconductor substrate“PWELL” of the cell are set at a potential “Vs” (1.6 V). In addition, apotential “VSG” (V_(DD)+Vth) (4 V), which allows an n-type MOStransistor to transfer a potential “V_(DD)” (2.5 V) to a gate “BLPRE”,is applied to “VPRE”. Then, a potential of 0.7 V+Vth+Vs is applied to agate “BLCLAMP”. Thus, the potential at the gate “BLSe” controlled by thecontrol circuit 7 is raised to “High”, and the selected bit line “BLe”is pre-charged to a potential of 0.7 V+Vs (=2.3 V).

After the pre-charge, the potential at the gate “BLCLAMP” is set at 0 V,thereby separating the bit lines “BL” and the sense amplifier 3.

Furthermore, a potential “VCGRV” is applied to the word line “WL” to beread (“CG-sel”), and a potential “VREAD” (6.5 V), which allows turn-onwithout fail, is applied to the other word lines “WL” (“CG-usel”) andthe drain-side select gate line “SGD”. Then, a potential “VREAD” isapplied to the source-side select gate line “SGS”.

Thus, if a cell to be read is turned on (the case where cell read is inon state), a cell current flows, and the bit line “BLe” is broughtcloser to the potential Vs.

On the other hand, if a cell to be read is turned off (the case wherecell read is in off state), no cell current flows, and the bit line“BLe” remains at the pre-charge potential (0.7 V+Vs).

The potential “VPRE” and the potential at the gate “BLPRE” are raisedagain to pre-charge the node “TDC” to the potential “V_(DD)”.Furthermore, “BOOST” is raised to raise the potential at the node “TDC”to about 4.5 V by capacitive coupling. Then, the potential at the gate“BLCLAMP” is set at a potential “VSEN” (0.5 V+Vth+Vs).

Compared with the capacitance of the bit line “BL”, the capacitance ofthe node “TDC” is small. Therefore, when the cell is turned on (the caseof on cell), if the potential of the bit line “BLe” is lower than 0.5V+Vs, charge sharing occurs, and the potential at the not “TDC” becomesequal to the potential of the bit line “BLe”.

When the cell is turned off (the case of off cell), if the potential ofthe bit line “BL” is equal to 0.7 V+Vs, the voltage applied to the gate“BLCLAMP” cannot exceed the threshold of the transistor 3 b. Thus, thetransistor 3 b remains in the off state, and the potential at the node“TDC” remains at 4.5 V.

Then, after the potential at the gate “BLCLAMP” is temporarily raised,“BOOST” is lowered while a voltage “VTR” (1.2 V) slightly higher thanthe threshold of the transistor 3 b having the gate “BLCLAMP” is beingapplied.

As a result, the potential at the node “TDC” is lowered due tocapacitive coupling. The potential at the node “TDC” connected to theturned-on cell is lowered to approach 0 V. The potential at the node“TDC” connected to the turned-off cell returns to “V_(DD)”.

Then, the potential at a gate “BLC1” is raised to transfer the potentialat the node “TDC” to the latch circuit 3 a, thereby designating H/L.

Through the operation described above, reading of the NAND flash memory100 is achieved while the selected bit line “BLe” and the non-selectedbit line “BLo” are adjacent to each other.

The potential of the non-selected bit line “BLo”, which is not selectedas a result of the potential at the gate “BLSo” being kept at “Low”under the control of the control circuit 7, is set at Vs (1.6 V) whenthe potential at “BIASo” is raised to “High” under the control of thecontrol circuit 7.

FIG. 5 is a diagram showing a configuration of essential parts includinga voltage generating circuit that applies the voltage Vs.

As shown in FIG. 5, a voltage generating circuit 10 is connected to thesource line “CELSRC”, the control line “BLCRL”, the p-type well “PWELL”and the n-type well of the cell via a switch circuit 11 havingtransistors 11 a, 11 b and 11 c. The voltage generating circuit 10applies the voltage “Vs” to the source line “CELSRC” of the cell, thecontrol line “BLCRL” connected to the bit line (shielded bit line) “BLo”not selected in FIG. 3, and the p-type well “PWELL” and n-type well“NWELL” by turning on the transistors 11 a, 11 b and 11 c, respectively.

In addition, after the voltage “Vs” is applied, the source line “CELSRC”of the cell, the non-selected bit line (shielded bit line) “BLo”, andthe p-type well “PWELL” and n-type well “NWELL” can be brought into thefloating state by turning off the transistors 11 a, 11 b and 11 c,respectively.

Now, the amount of charge required to charge the bit line in the readingoperation described above will be discussed.

FIG. 6A is a graph showing a relationship between time and voltageapplied to the selected bit line or the like of the NAND flash memory100 during the reading operation according to the First Embodiment. FIG.6B is a graph showing another relationship between time and voltageapplied to the selected bit line or the like of the NAND flash memory100 during the reading operation according to the First Embodiment. FIG.7 is a diagram showing a model of a cross-sectional structure of theNAND flash memory 100. FIG. 8 is a diagram showing potentials at theparts of the NAND flash memory 100 shown in FIG. 7 and capacitancesbetween the parts.

As shown in FIG. 6A and FIG. 4 described above, the drain-side selectgate line “SGD”, the source-side select gate line “SGS” and the p-typesemiconductor substrate “Psub” of the block not selected by the rowdecoder 2 are set at a ground potential “Vss”. In addition, the sourceline “CELSRC”, the p-type well “PWELL” and the n-type well “NWELL” ofthe cells of the non-selected block, and the bit line (shielded bitline) “BLo” not selected by the sense amplifier 3 are brought into thefloating state (the potential “Vs”). In this state, the bit line “BLe”selected by the sense amplifier 3 is charged to “Vb” (2.3 V). The wordlines “WL” of the non-selected block are in the floating state.

The parts of the NAND flash memory 100 are arranged as shown in FIG. 7.As shown in FIG. 8, capacitances between the parts are denoted by “C1”(a combined capacitance of “C1 a”, “C1 b”, “C1 c” and “C1 d”), “C2” (acombined capacitance of “C2 a”, “C2 b”, “C2 c” and “C2 d”) and “C3”. InFIG. 8, the control gate is included in the select gate line SG.Furthermore, in FIG. 8, illustration of the word lines “WL” and thefloating gates FG (in FIG. 7) of the non-selected block in the floatingstate is omitted, because the effect thereof on the change in potentialis small.

The source line “CELSRC”, the p-type well “PWELL”, the n-type well“NWELL” and the non-selected bit line of the cell converges to apotential “Vs'”, which is determined by the coupling ratio.

${Vs}^{\prime} = {{Vb}\left( \frac{C\; 1}{{C\; 1} + {C\; 2}} \right)}$

Thus, the amount of charge “Q required for charging to “Vs”, that is,required for charging the bit line “BLe” to “Vb” can be considered as aseries capacitance. Thus, the amount of charge “Q” can be expressed asfollows (FIG. 8).

$Q = {{Vb}\left( {\frac{C\; 1C\; 2}{{C\; 1} + {C\; 2}} + {C\; 3}} \right)}$

Where, supposing that “C1”=130 nF, “C2”=50 nF, “C3”=10 nF and “Vb”=2.3V, “Vs'”=1.66 V, and “Q”=106 nC.

Now, there will be discussed a case similar to the prior art describedearlier where only the selected bit line is charged without charging thesource line “CELSRC”, the p-type well “PWELL”, the n-type well “NWELL”and the non-selected bit line “BLo” of the cell.

For example, supposing that the bit line charge potential is “Vb”, andthe bit line capacitance is (C1+C3), the required amount of charge isVb*(C1+C3). Supposing that “Vb”=0.7 V, and C1+C3=140 nF, the amount ofcharge required to charge the bit line is 98 nC.

Furthermore, there will be discussed a case similar to the prior artwhere the selected bit line is charged after the source line “CELSRC”,the p-type well “PWELL”, the n-type well “NWELL” and the non-selectedbit line “BLo” of the cell are charged.

For example, if it is supposed that the potential of the p-typesemiconductor substrate “Psub” and the non-selected select gate is“V_(SS)”, and the word lines “WL” of the non-selected block are in thefloating state, the other nodes are charged to “Vs” (the word lines “WL”and select gate line of the selected block are ignored because theeffect thereof is extremely small). The amount of charge required forthis charging is Vs*(C2+C3). The amount of charge required to charge thebit line is (Vb−Vs)*(C1+C3). Supposing that “Vs'”=1.6 V, “Vb”=2.3 V,C2+C3=60 nF, and C1+C3=140 nF, the total amount of charge is 194 nC (=96nC+98 nC). The required amount of charge is doubled by biasing thesource line “CELSRC”, the p-type well “PWELL” and the n-type well“NWELL” of the cell.

As described above, in this embodiment, the amount of charge “Q requiredto charge the selected bit line “BLe” of the non-selected block to “Vb”depends on the ratio between the capacitances “C1” and “C2”. However,compared with a case where the selected bit line is charged after thesource line “CELSRC”, the p-type well “PWELL”, the n-type well “NWELL”and the non-selected bit line “BLo” of the cell are charged in thenon-selected block, the required amount of charge “Q can beapproximately halved if “Vs'” determined by the coupling ratio is closeto a target.

Furthermore, even compared with a case where only the selected bit lineis charged without charging the source line “CELSRC”, the p-type well“PWELL”, the n-type well “NWELL” and the non-selected bit line “BLo” ofthe cell, the required amount of charge is substantially the samealthough the amount slightly increases. Thus, charging can be completedin substantially the same time as a case where only the selected bitline is charged without charging the source line “CELSRC”, the p-typewell “PWELL”, the n-type well “NWELL” and the non-selected bit line“BLo” of the cell.

In this way, the threshold distribution of the cell can be formed notonly in the positive region but also in the negative region withoutsignificantly changing the required amount of charge and increasing thecharge time.

If the coupling ratio varies, the potential “Vs” is shifted from thetarget potential. Thus, in order to compensate for the shift, chargeexchange with the voltage generating circuit 10 that applies thepotential “Vs” is required.

Thus, as shown in FIG. 6B, in the block not selected by the row decoder2, the drain-side select gate line “SGD”, the source-side select gateline “SGS” and the p-type semiconductor substrate “Psub” are set at theground potential “V_(SS)”.

Furthermore, the source line “CELSRC”, the n-type well “NWELL”, thep-type well “PWELL”, and the bit line “BLo” not selected by the senseamplifier 3 may be charged by the voltage generating circuit 10 to “Vs”,which is a second potential, and at the same time, the bit line “BLe”selected by the sense amplifier 3 may be charged to “Vb”. Here, thesecond potential “Vs” is a potential between “Vb”, which is a firstpotential to which the bit line “BLe” selected by the sense amplifier 3is charged, and the ground potential “V_(SS)”.

Thus, since the potential “Vs” is controlled by the voltage generatingcircuit 10, the shift of the potential “Vs” from the target potentialcan be reduced.

As described above, for the NAND flash memory according to thisembodiment, the threshold distribution can be formed in the negativeregion while preventing an increase in current and pre-charge time.

Second Embodiment

In the First Embodiment, if the coupling ratio between the capacitances“C1” and “C2” shown in FIG. 8 varies, the potential “Vs” is shifted.Thus, to compensate for the shift, an additional amount of charge isrequired. A desired coupling ratio can be achieved by modifying thestructure itself, for example, adjusting the line width or the spacebetween the lines. However, it is actually difficult.

The function of the non-selected select gate transistor is to cut offthe bit line and the source line of the cell from each other. When thepotential of the source line of the cell is “Vs” in reading, if thepotential of the non-selected select gate line is equal to or lower than“Vs”, the cut-off can be achieved. That is, the potential “Vs”, which isdetermined by the coupling ratio, can be adjusted by applying apotential ranging from 0 V to “Vs” to the select gate line of thenon-selected block, thereby changing the capacitance of the select gateof the non-selected block.

Thus, in a Second Embodiment, there will be described an configurationin which the potential “Vs”, which is determined by the coupling ratio,is adjusted to a target value by applying a voltage to the select gateline of the non-selected block, thereby changing the capacitance of theselect gate of the non-selected block.

FIG. 9 is a circuit diagram showing a configuration of a NAND flashmemory 200 according to the Second Embodiment, which is an aspect of thepresent invention, including blocks and a row decoder. The entireconfiguration of the NAND flash memory 200 is the same as theconfiguration shown in FIG. 1.

As shown in FIG. 8, the NAND flash memory 200 has a voltage driver 204that supplies an adjustable voltage “VSGDS” to a row decoder 203.

If a transistor “TGs” of the row decoder 203 is turned on, and atransistor “TGsn” is turned off, a block 201 is selected (a selectedblock). As a result, voltages “VCG0” to “VCG2”, “VSGS” and “VSGD” aretransferred to selected word lines “WL0 s” to “WL2 s” and select gatelines “SGSs” and “SGDs”. As a result, the word lines and the select gatelines of the selected block 201 are turned on.

On the other hand, if a transistor “TGu” of the row decoder 204 isturned off, and a transistor “TGun” is turned on, a block 202 is notselected (a non-selected block). As a result, word lines “WL0 u” to “WL2u” are in the floating state. In addition, the potential “VSGDS” istransferred to non-selected select gate lines “SGSu” and “SGDu”.

The voltage driver 204 changes the potential “VSGDS” within a range inwhich the non-selected select gate lines “SGSu” and “SGDu” are cut off.That is, to the drain-side select gates and the source-side select gatesof the transistors of the block not selected by the row decoder 2, thevoltage driver 204 applies a potential equal to or lower than athreshold of the transistors.

With such a configuration, the coupling ratio between the capacitances“C1” and “C2” shown in FIG. 8 in the First Embodiment can be adjusted.By adjusting the coupling ratio, the potential “Vs”, which is determinedby the coupling ratio, can also be adjusted to a target value.

As described above, for the NAND flash memory according to thisembodiment, the threshold distribution can be formed in the negativeregion while preventing an increase in current and pre-charge time, asin the First Embodiment. In addition, the potential “Vs”, which isdetermined by the coupling ratio, can be adjusted by changing thecapacitance of the select gate lines of the non-selected block.

Third Embodiment

In the First Embodiment, the non-selected word lines are set in thefloating state. The coupling ratio between the capacitance “C1” and “C2”shown in FIG. 8 in the First Embodiment can be changed by applying apotential to the non-selected word lines.

Thus, in a Third Embodiment, there will be described a configuration inwhich a potential is applied to the non-selected word lines.

FIG. 10 is a circuit diagram showing a configuration of a NAND flashmemory 300 according to the Third Embodiment of the present invention,which is an aspect of the present invention, including blocks and a rowdecoder.

FIG. 10 shows an example in which row decoders 303 and 304 are disposedon the opposite sides of a memory cell array 1. The left-hand row driver303 and the right-hand row decoder 304 have a left-hand driver 305 and aright-hand driver 306 for a control gate and a select gate,respectively. Thus, there is no need of increasing the area of the rowdecoder 2.

For example, if a block 301 is selected by the left-hand row decoder303, a transistor “TGs” of the selected block 301 is turned on, and atransistor “TGsn” is turned off. As a result, voltages “VCG0_L” to“VCG2_L” are applied by the left-hand driver 305 to word lines “WL0 us”to “WL0 us”. In addition, voltages “VSGS_L” and “VSGD_L” are applied bythe left-hand driver 305 to a source-side select gate line “SGSus” and adrain-side select gate line “SGDus”.

Furthermore, in a non-selected left-hand block 307, which is notselected by the left-hand row decoder 303, a transistor “TguL” is turnedoff, and a transistor “TGunL” is turned on. As a result, word lines “WL0uL” to “WL0 uL” are in the floating state, and a voltages “VSGDS_L” isapplied by the left-hand driver 305 to a source-side select gate line“SGSuL” and a drain-side select gate line “SGDuL”.

On the other hand, in a non-selected block 302, which is not selected bythe right-hand row decoder 304, a transistor “TGuR” is turned on, and atransistor “TGunR” is turned off. As a result, voltages “VCG0_R” to“VCG2_R” are applied by the right-hand driver 306 to word lines “WL0 uR”to “WL2 uR”. In addition, voltages “VSGS_R” and “VSGD_R” (instead of avoltage “VSGDS_R”) are applied by the right-hand driver 306 to asource-side select gate line “SGSuR” and a drain-side select gate line“SGDuR”.

The coupling ratio between the capacitances “C1” and “C2” shown in FIG.1 in the First Embodiment can be changed by adjusting the voltages“VCG0_R” to “VCG0_R” to an appropriate voltage, or in other words, byapplying a potential to the word lines “WL” of the block not selected bythe row decoder.

In this way, a target coupling ratio can be achieved by changing thepotential of the non-selected word lines.

As described above, for the NAND flash memory according to thisembodiment, as in the First Embodiment, the threshold distribution canbe formed in the negative region while preventing an increase in currentand pre-charge time.

Furthermore, the potential “Vs”, which is determined by the couplingratio, can be adjusted by changing the capacitance of the select gatelines of the non-selected block.

Fourth Embodiment

In the First Embodiment, as an example, there has been described aconfiguration in which the potential “Vb” of the selected bit line israised at the same time as the potential “Vs” being raised.

In an Fourth Embodiment, there will be described a configuration inwhich the potential “Vb” of the selected bit line is raised while thepotential “Vs” is being raised.

FIG. 11 is a circuit diagram showing a push-pull circuit, which is avoltage generating circuit used in the Fourth Embodiment of the presentinvention. FIG. 12 is a graph showing a relationship between time andvoltage applied to a selected bit line or the like of a NAND flashmemory 100 during reading operation according to the Fourth Embodiment.

As shown in FIG. 11, a push-pull circuit 400 has a first p-type MOStransistor 402 that is connected to a power supply “V_(DD)” at thesource thereof and to an output terminal 401 for outputting a voltage“Vs” at the drain thereof, and a first n-type MOS transistor 403 that isconnected between the drain of the first p-type MOS transistor 402 and aground potential.

Furthermore, the push-pull circuit 400 has a voltage dividing circuit404 that is composed of a voltage-dividing resistors “Rx” and “R0” anddivides the potential at the output terminal 401, and a first comparator405 that receives the potential at the output terminal 401 at theinverting input terminal thereof and a reference voltage “VSRCREF” atthe non-inverting input terminal thereof, compares these inputs andoutputs a signal to the gate of the first p-type MOS transistor 402.

Furthermore, the push-pull circuit 400 has a second p-type MOStransistor 406 that is connected to the power supply “V_(DD)” at thesource thereof, and a second n-type MOS transistor 407 that is connectedto the drain of the second p-type MOS transistor 406 at the drainthereof, to the drain thereof and the gate of the first n-type MOStransistor 403 at the gate thereof, and to the ground potential at thesource thereof.

Furthermore, the push-pull circuit 400 has a second comparator 408 thatreceives the reference voltage “VSRCREF” at the inverting input terminalthereof and a voltage divided output of the voltage dividing circuit 404at the non-inverting input terminal, compares these inputs, and outputsa signal to the gate of the second p-type MOS transistor 406.

Now, an operation of the push-pull circuit 400 configured as describedabove will be described.

If the voltage “Vs” of the push-pull circuit 400 is lower than thereference voltage “VSRCREF”, a charging operation is conducted byturning on the first p-type MOS transistor 402 and turning off the firstn-type MOS transistor.

If the output voltage “Vs” of the push-pull circuit 400 is higher than

${\left( \frac{{R\; 0} + {Rx}}{R\; 0} \right){VSRCREF}},$

a discharging operation is conducted by turning off the first p-type MOStransistor 402 and turning on the first n-type MOS transistor 403.

If the output voltage “Vs” of the push-pull circuit 400 is higher thanthe reference voltage “VSRCREF” and lower than

${\left( \frac{{R\; 0} + {Rx}}{R\; 0} \right){VSRCREF}},$

the first N-type MOS transistor 403 and the first p-type MOS transistor402 are turned off, and thus the push-pull circuit 400 enters into thedead band. The dead band is necessary because a through current flows ifthe threshold of the transistor varies.

Now, as in the First Embodiment, it is supposed that the selected bitline is charged with the source line, the p-type well and thenon-selected bit line (shielded bit line) of the cell being in thefloating state. In this case, if the voltage

${{Vs} = {{Vb}\left( \frac{C\; 1}{{C\; 1} + {C\; 2}} \right)}},$

which is determined by the coupling ratio, converges to the dead band,the output voltage “Vs” may be indeterminable within a range

$\left( {{VSRCREF} < {Vs} < {\left( \frac{{R\; 0} + {Rx}}{R\; 0} \right){VSRCREF}}} \right).$

Thus, instead of charging the selected bit line “BLe” with the sourceline, the p-type semiconductor substrate and the non-selected bit line(shielded bit line) “BLo” of the cell being in the floating state, thepush-pull circuit 400 for the power supply “Vs” for the source line, thep-type semiconductor substrate and the shielded bit line of the cell isturned on slightly earlier than charging of the selected bit line (FIG.12).

That is, in a block not selected by a row decoder 2, the drain-sideselect gate line “SGD”, the source-side select gate line “SGS” and thep-type semiconductor substrate “Psub” are set at the ground potential“V_(SS)”.

Furthermore, while the source line “CELSRC”, the n-type well “NWELL”,the p-type well “PWELL” and the bit line “BLo” not selected by the senseamplifier 3 are being charged to the second potential “Vs” by thevoltage generating circuit 10, the bit line “BLe” selected by the senseamplifier 3 is charged to the first potential “Vb”. As described above,the second potential “Vs” is a potential between the first potential“Vb” to which the bit line “BLe” selected by the sense amplifier 3 ischarged and the ground potential “V_(SS)”.

Thus, the second potential “Vs”, which is determined by the couplingratio, is expressed as follows.

${Vs} = {{{Vb}\left( \frac{C\; 1}{{C\; 1} + {C\; 2}} \right)} + \alpha}$

In this formula, reference character α represents an initial chargepotential, which occurs as a result of the generator for the potential“Vs” being turned on slightly earlier than charging of the selected bitline.

If the condition

$\left( {{{Vb}\left( \frac{C\; 1}{{C\; 1} + {C\; 2}} \right)} + \alpha} \right) < \left( {\left( \frac{{R\; 0} + {Rx}}{R\; 0} \right){VSRCREF}} \right)$

is satisfied, the first n-type MOS transistor 407 of the push-pullcircuit is turned off after the potential determined by the couplingratio settles. As a result, a discharge operation occurs, and thepotential “Vs” converges to the following value.

${Vs} = {\left( \frac{{R\; 0} + {Rx}}{R\; 0} \right){VSRCREF}}$

By conducting charging to “Vs” in advance, the required amount of chargemay increase compared with a case where charging to “Vs” is conducted inthe floating state.

However, compared with a case where charging to “Vs” is completelyconducted, the amount of charge can be reduced. The pre-charge timeincreases only slightly.

Furthermore, within the set-up period of “Vb”, the operating time of theNAND flash memory does not increase due to the pre-charge time.

As described above, for the NAND flash memory according to thisembodiment, as in the First Embodiment, the threshold distribution canbe formed in the negative region while preventing an increase in currentand pre-charge time.

1. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising a memory cell array having a plurality of blocks each including a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and disposed on a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof; wherein a first bit line that is selected is charged to a first potential while the p-type semiconductor substrate is being set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are being charged to a second potential that is between said first potential and said ground potential at the same time as the select bit line is charged.
 2. The NAND flash memory according to claim 1, wherein a third potential equal to or lower than thresholds of the drain-side select gate transistor and the source-side select gate transistor is applied to the drain-side select gate line and the source-side select gate line of a block that is not selected.
 3. The NAND flash memory according to claim 1, wherein a third potential is applied to the word lines of said block that is not selected.
 4. The NAND flash memory according to claim 3, wherein a fourth potential is applied to the word lines of said block that is not selected.
 5. The NAND flash memory according to claim 1, further comprising, a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array, and applies signal voltages to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array for selecting the blocks; and a sense amplifier that is connected to the bit lines of the memory cell array.
 6. The NAND flash memory according to claim 5, wherein the sense amplifier includes: a first transistor having a first end connected to the first bit line; and a second transistor having a first end connected to the second bit line, a second end of the first transistor being connected to a second end of the second transistor.
 7. The NAND flash memory according to claim 1, wherein the first bit line is adjacent to the second bit line.
 8. The NAND flash memory according to claim 6, wherein the first bit line is selected by the first transistor turning on, and the second bit line is not selected by the second transistor turning off.
 9. The NAND flash memory according to claim 1, further comprising transistors respectively having a first end and a second end, the first ends of the transistors connected to the source lines, the n-type wells, and the p-type wells respectively, and the second ends of the transistors connected with each other.
 10. The NAND flash memory according to claim 9, wherein the second ends of the transistors are connected to a voltage generating circuit.
 11. The NAND flash memory according to claim 6, wherein the second end of the first transistor and the second end of the second transistor are connected to a power supply voltage. 